EP2C8T144C8N Datasheet, PDF (298/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Supported I/O Standards
Figure 10–15. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V VTT = 0.75 V
Differential
Transmitter
50 Ω
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
Figure 10–16. 1.5-V Differential HSTL Class II Termination
V_TT = 0.75 V V_TT = 0.75 V
V_TT = 0.75 V V_TT = 0.75 V
Differential
Transmitter
50 Ω
50 Ω
50 Ω
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
LVDS, RSDS and mini-LVDS
The LVDS standard is formulated under ANSI/TIA/EIA Standard,
ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage
Differential Signaling Interface Circuits.
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard. This standard is
used in applications requiring high-bandwidth data transfer, backplane
drivers, and clock distribution. Cyclone II devices are capable of running
at a maximum data rate of 805 Mbps for input and 640 Mbps for output
and still meet the ANSI/TIA/EIA-644 standard.
Because of the low voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than
complementary metal-oxide semiconductor (CMOS),
10–16
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008