EP2C8T144C8N Datasheet, PDF (343/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

12. Embedded Multipliers in
Cyclone II Devices
CII51012-1.2
Introduction
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Use Cyclone^® II FPGAs alone or as digital signal processing (DSP)
co-processors to improve price-to-performance ratios for DSP
applications. You can implement high-performance yet low-cost DSP
systems with the following Cyclone II device features and design
support:
■ Up to 150 18 x 18 multipliers
■ Up to 1.1 Mbit of on-chip embedded memory
■ High-speed interface to external memory
■ DSP Intellectual Property (IP) cores
■ DSP Builder interface to the Mathworks Simulink and Matlab design
environment
■ DSP Development Kit, Cyclone II Edition
This chapter focuses on the Cyclone II embedded multiplier blocks.
Cyclone II devices have embedded multiplier blocks optimized for
multiplier-intensive low-cost DSP applications. These embedded
multipliers combined with the flexibility of programmable logic devices
(PLDs), provide you with the ability to efficiently implement various cost
sensitive DSP functions easily. Consumer-based application systems such
as digital television (DTV) and home entertainment systems typically
require a cost effective solution for implementing multipliers to perform
signal processing functions like finite impulse response (FIR) filters, fast
Fourier transform (FFT) functions, and discrete cosine transform (DCT)
functions.
Along with the embedded multipliers, the M4K memory blocks in
Cyclone II devices also support various soft multiplier implementations.
These, in combination with the embedded multipliers increase the
available number of multipliers in Cyclone II devices and provide the
user with a wide variety of implementation options and flexibility when
designing their systems.
See the Cyclone II Device Family Data Sheet section in Volume 1 of the
Cyclone II Device Handbook for more information on Cyclone II
devices.
Altera Corporation
February 2007
12–1