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EP2C8T144C8N Datasheet, PDF (253/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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Cyclone II Memory Blocks
Document
Table 8â8 shows the revision history for this document.
Revision History
Table 8â8. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
February 2008
v2.4
February 2007
v2.3
Corrected Figure 8â12.
â Added document revision history.
â Updated âPacked Mode Supportâ section.
â Updated âMixed-Port Read-During-Write Modeâ section
and added new Figure 8â24.
â
â In packed mode support,
the maximum data width for
each of the two memory
block is 18 bits wide.
â Added donât care mode
information to mixed-port
read-during-write mode
section.
November 2005 Updated Figures 8â13 through 8â20.
â
v2.1
July 2005 v2.0 Added Clear Signals section.
â
February 2005 Added a note to Figures 8-13 through 8-20 regarding
â
v1.1
violating the setup and hold time on address registers.
June 2004 v1.0 Added document to the Cyclone II Device Handbook.
â
Altera Corporation
February 2008
8â31
Cyclone II Device Handbook, Volume 1
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