EP2C8T144C8N Datasheet, PDF (408/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

JTAG Configuration
A device operating in JTAG mode uses the TDI, TDO, TMS, and TCK pins.
The TCK pin has a weak internal pull-down resistor while the other JTAG
input pins, TDI and TMS, have weak internal pull-up resistors. All user
I/O pins are tri-stated during JTAG configuration. Table 13–9 explains
each JTAG pin's function.
Table 13–9. Dedicated JTAG Pins
Pin Name
TDI
TDO
TMS
TCK
Pin Type
Description
Test data input
Serial input pin for instructions as well as test
and programming data. Data is shifted in on
the rising edge of TCK.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
connecting this pin to V_{C C}.
Test data
output
Serial data output pin for instructions as well as
test and programming data. Data is shifted out
on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
leaving this pin unconnected.
Test mode
select
Input pin that provides the control signal to
determine the transitions of the TAP controller
state machine. Transitions within the state
machine occur on the rising edge of TCK.
Therefore, TMS must be set up before the
rising edge of TCK. TMS is evaluated on the
rising edge of TCK.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
connecting this pin to V_{C C}.
Test clock
input
The clock input to the BST circuitry. Some
operations occur at the rising edge, while
others occur at the falling edge.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
connecting this pin to GND.
1
The TDO output is powered by the V_CCIO power supply. If V_CCIO
is tied to 3.3-V, both the I/O pins and the JTAG TDO port drive
at 3.3-V levels.
13–54
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007