EP2C8T144C8N Datasheet, PDF (367/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Figure 13–4. Multiple Device AS Configuration
V_CC (1) V_CC (1) V_CC (1)
10 kΩ 10 kΩ 10 kΩ
Configuring Cyclone II Devices
V_CC (2)
10 kΩ
Serial Configuration
Device
DATA
DCLK
nCS
ASDI
GND
Cyclone II FPGA
Master Device
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
DATA0
DCLK
nCSO
ASDO
MSEL1
MSEL0
V_CC
GND
Cyclone II FPGA
Slave Device
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
DATA0
DCLK
MSEL1
MSEL0
N.C. (3)
V_CC
GND
Notes to Figure 13–4:
(1) Connect the pull-up resistors to a 3.3-V supply.
(2) Connect the pull-up resistor to the V_CCIO supply voltage of I/O bank that the nCEO pin resides in.
(3) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCE pin.
As shown in Figure 13–4, the nSTATUS and CONF_DONE pins on all target
FPGAs are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the FPGAs. When the first device
asserts nCEO (after receiving all of its configuration data), it releases its
CONF_DONE pin. However, the subsequent devices in the chain keep the
CONF_DONE signal low until they receive their configuration data. When
all the target FPGAs in the chain have received their configuration data
and have released CONF_DONE, the pull-up resistor pulls this signal high,
and all devices simultaneously enter initialization mode.
Altera Corporation
February 2007
13–13
Cyclone II Device Handbook, Volume 1