EP2C8T144C8N Datasheet, PDF (324/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II High-Speed I/O Banks
pins in each I/O bank (on both rows and columns) support the high-
speed I/O interface. Cyclone II pin tables list the pins that support the
high-speed I/O interface.
Figure 11–1. I/O Banks in EP2C5 & EP2C8 Devices
I/O Bank 2 Also Supports
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
I/O Bank 2
I/O Bank 1
Also Supports the
3.3-V PCI & PCI-X
I/O Standards
I/O Bank 1
All I/O Banks Support
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
■ LVDS
■ RSDS
■ mini-LVDS
■ LVPECL (1)
■ SSTL-2 Class I and II
■ SSTL-18 Class I
■ HSTL-18 Class I
■ HSTL-15 Class I
■ Differential SSTL-2 (2)
■ Differential SSTL-18 (2)
■ Differential HSTL-18 (3)
■ Differential HSTL-15 (3)
Individual
Power Bus
I/O Bank 3
Also Supports the
3.3-V PCI & PCI-X
I/O Standards
I/O Bank 3
I/O Bank 4
I/O Bank 4 Also Supports
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
Notes to Figure 11–1:
(1) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(2) The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(3) The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
11–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007