EP2C8T144C8N Datasheet, PDF (231/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
1 M4K memory blocks do not support asynchronous memory
(unregistered inputs).
The M4K memory blocks support the following modes:
■ Single-port
■ Simple dual-port
■ True dual-port (bidirectional dual-port)
■ Shift register
■ ROM
■ FIFO buffers
1 Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
Single-Port Mode
Single-port mode supports non-simultaneous read and write operations.
Figure 8–6 shows the single-port memory configuration for Cyclone II
memory blocks.
Figure 8–6. Single-Port Mode Note (1)
data[ ]
address[ ]
wren
byteena[ ]
addressstall
inclock
inclocken
q[ ]
outclock
outclocken
outaclr
Note to Figure 8–6:
(1) Two single-port memory blocks can be implemented in a single M4K block in
packed mode.
f
In single-port mode, the outputs are in read-during-write mode, which
means that during the write operation, data written to the RAM flows
through to the RAM outputs. When the output registers are bypassed, the
new data is available on the rising edge of the same clock cycle on which
it was written.
See “Read-During- Write Operation at the Same Address” on page 8–28
for more information about read-during-write mode.
The port width configurations for M4K blocks in single-port mode are as
follows:
Altera Corporation
February 2008
8–9
Cyclone II Device Handbook, Volume 1