EP2C8T144C8N Datasheet, PDF (234/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Memory Modes
address. See “Read-During- Write Operation at the Same Address” on
page 8–28 for more information. Figure 8–9 shows timing waveforms for
read and write operations in simple dual-port mode.
Figure 8–9. Cyclone II Simple Dual-Port Timing Waveforms
wrclock
wren
wraddress
an-1
an
a0
a1
a2
data (1)
din-1
din
rdclock
rden
rdaddress
bn
q (synch) doutn-2
b0
doutn-1
b1
doutn
q (asynch) doutn-1
doutn
dout0
Note to Figure 8–9:
(1) The crosses in the data waveform during read mean “don’t care.”
a3
a4
din4
b2
dout0
a5
a6
din5
din6
b3
True Dual-Port Mode
True dual-port mode supports any combination of two-port operations:
two reads, two writes, or one read and one write at two different clock
frequencies. Figure 8–10 shows Cyclone II true dual-port memory
configuration.
8–12
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008