EP2C8T144C8N Datasheet, PDF (419/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Configuring Cyclone II Devices
Table 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 2 of 5)
Pin Name
nSTATUS
User Configuration
Mode Scheme
Pin Type
N/A All
Bidirectional
open-drain
Description
The Cyclone II device drives nSTATUS low
immediately after power-up and releases it after the
POR time.
This pin provides a status output and input for the
Cyclone II device. If the Cyclone II device detects an
error during configuration, it drives the nSTATUS pin
low to stop configuration. If an external source (for
example, another Cyclone II device) drives the
nSTATUS pin low during configuration or
initialization, the target device enters an error state.
Driving nSTATUS low after configuration and
initialization does not affect the configured device. If
your design uses a configuration device, driving
nSTATUS low causes the configuration device to
attempt to configure the FPGA, but since the FPGA
ignores transitions on nSTATUS in user mode, the
FPGA does not reconfigure. To initiate a
reconfiguration, pull the nCONFIG pin low.
The enhanced configuration devices’ and EPC2
devices’ OE and nCS pins are connected to the
Cyclone II device’s nSTATUS and CONF_DONE pins,
respectively, and have optional internal
programmable pull-up resistors. If you use these
internal pull-up resistors on the enhanced
configuration device, do not use external 10-kΩ pull-
up resistors on these pins. When using EPC2
devices, you should only use external 10-kΩ pull-up
resistors.
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
Altera Corporation
February 2007
13–65
Cyclone II Device Handbook, Volume 1