EP2C8T144C8N Datasheet, PDF (204/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Hardware Features
Manual Clock Switchover
The Cyclone II PLLs support manual switchover of the reference clock
through internal logic. This enables you to switch between two reference
input clocks. Use this feature for a dual clock domain application such as
in a system that turns on the redundant clock if the primary clock stops
running.
Figure 7–10 shows how the PLL input clock (f_IN) is generated from one of
four possible clock sources. The first stage multiplexing consists of two
dedicated multiplexers that generate two single-ended or two differential
clocks from four dedicated clock pins. These clock signals are then
multiplexed to generate f_IN by using another dedicated 2-to-1
multiplexer. The first stage multiplexers are controlled by configuration
bit settings in the configuration file generated by the Quartus II software,
while the second stage multiplexer is either controlled by the
configuration bit settings or logic array signal to allow the f_IN to be
controlled dynamically. This allows the implementation of a manual
clock switchover circuit where the PLL reference clock can be switched
during user mode for applications that requires clock redundancy.
Figure 7–10. Cyclone II PLL Input Clock Generation
(1)
inclk1
CLK[n + 3]
(2)
f_IN
CLK[n + 2]
CLK[n + 1]
inclk0
(1)
CLK[n]
Notes to Figure 7–10:
(1) This select line is set through the configuration file.
(2) This select line can either be set through the configuration file or it can be
dynamically set in user mode when using the manual switchover feature.
7–20
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007