EP2C8T144C8N Datasheet, PDF (442/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Using IEEE Std. 1149.1 BST Circuitry
Figure 14–13. JTAG Chain of Mixed Voltages
Must be
3.3 V
tolerant
TDI
3.3 V
V_CCIO
2.5 V
V_CCIO
Tester
TDO
Level
Shifter
1.5 V
V_CCIO
1.8 V
V_CCIO
Shift TDO to
level accepted by
tester if necessary
Must be
1.8 V
tolerant
Must be
2.5 V
tolerant
Using IEEE Std.
1149.1 BST
Circuitry
Cyclone II devices have dedicated JTAG pins, and the IEEE Std. 1149.1
BST circuitry is enabled upon device power-up. You can perform BST on
Cyclone II FPGAs not only before and after configuration, but also during
configuration. Cyclone II FPGAs support the BYPASS, IDCODE, and
SAMPLE instructions during configuration without interrupting
configuration. To send all other JTAG instructions, you must interrupt
configuration using the CONFIG_IO instruction.
The CONFIG_IO instruction allows you to configure I/O buffers via the
JTAG port, and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Cyclone II FPGA or waiting for a configuration device to complete
configuration. Once configuration has been interrupted and JTAG BST is
complete, the part must be reconfigured via JTAG (PULSE_CONFIG
instruction) or by pulsing nCONFIG low.
When you perform JTAG boundary-scan testing before configuration, the
nCONFIG pin must be held low.
The device-wide reset (DEV_CLRn) and device-wide output enable
(DEV_OE) pins on Cyclone II devices do not affect JTAG boundary-scan or
configuration operations. Toggling these pins does not disrupt BST
operation any more than usual.
14–16
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007