EP2C8T144C8N Datasheet, PDF (334/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

I/O Standards Support
Figure 11–11. LVPECL I/O Interface
LVDS Transmitter
Z = 50 Ω
Z = 50 Ω
100 Ω
Cyclone II Receiver
f
Differential SSTL Support in Cyclone II Devices
The differential SSTL I/O standard is a memory bus standard used for
applications such as high-speed double data rate (DDR) SDRAM
interfaces. The differential SSTL I/O standard is similar to voltage
referenced SSTL and requires two differential inputs with an external
termination voltage (V_TT) of 0.5 × V_CCIO to which termination resistors
are connected. A 2.5-V output source voltage is required for differential
SSTL-2, while a 1.8-V output source voltage is required for differential
SSTL-18. The differential SSTL output standard is only supported at
PLLCLKOUT pins using two single-ended SSTL output buffers
programmed to have opposite polarity.
The differential SSTL input standard is supported at the global clock
(GCLK) pins only, treating differential inputs as two single-ended SSTL,
and only decoding one of them.
For SSTL signaling characteristics, see the DC Characteristics & Timing
Specification chapter and the Selectable I/O Standards in Cyclone II Devices
chapter in Volume 1 of the Cyclone II Device Handbook.
Figures 11–12 and 11–13 show the differential SSTL class I and II
interfaces, respectively.
11–12
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007