EP2C8T144C8N Datasheet, PDF (316/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

5.0-V Device Compatibility
Table 10–12. Cyclone II I/O Standard DC Current Specification (Preliminary) (Part 2 of 2)
I/O Standard
1.5-V differential HSTL class II (3)
LVDS, RSDS and mini-LVDS
I_PIN (mA)
Top and Bottom Banks
16 (4)
12
Side Banks
12
Notes to Table 10–12:
(1) The DC power specification of each I/O standard depends on the current sourcing and sinking capabilities of the
I/O buffer programmed with that standard, as well as the load being driven. LVTTL and LVCMOS, and 2.5-, 1.8-,
and 1.5-V outputs are not included in the static power calculations because they normally do not have resistor
loads in real applications. The voltage swing is rail-to-rail with capacitive load only. There is no DC current in the
system.
(2) This I_PIN value represents the DC current specification for the default current strength of the I/O standard. The I_PIN
varies with programmable drive strength and is the same as the drive strength as set in Quartus II software. Refer
to the Cyclone II Architecture chapter in volume 1 of the Cyclone II Device Handbook for more information on the
programmable drive strength feature of voltage referenced I/O standards.
(3) The current value obtained for differential HSTL and differential SSTL standards is per pin and not per differential
pair, as opposed to the per-pair current value of LVDS standard.
(4) This I/O standard is only supported for clock input pins and PLL_OUT pins.
Table 10–12 only shows the limit on the static power consumed by an I/O
standard. The amount of total power used at any moment could be much
higher, and is based on the switching activities.
5.0-V Device
Compatibility
A Cyclone II device may not correctly interoperate with a 5.0-V device if
the output of the Cyclone II device is connected directly to the input of the
5.0-V device. If V_OUT of the Cyclone II device is greater than V_CCIO, the
PMOS pull-up transistor still conducts if the pin is driving high,
preventing an external pull-up resistor from pulling the signal to 5.0-V.
A Cyclone II device can drive a 5.0-V LVTTL device by connecting the
V_CCIO pins of the Cyclone II device to 3.3 V. This is because the output
high voltage (V_OH) of a 3.3-V interface meets the minimum high-level
voltage of 2.4-V of a 5.0-V LVTTL device. (A Cyclone II device cannot
drive a 5.0-V LVCMOS device.)
Because the Cyclone II devices are 3.3-V, 64- and 32-bit, 66- and 33-MHz
PCI and 64-bit 133-MHz PCI-X compliant, the input circuitry accepts a
maximum high-level input voltage (V_IH) of 4.1-V. To drive a Cyclone II
device with a 5.0-V device, you must connect a resistor (R₂) between the
Cyclone II device and the 5.0-V device. Refer to Figure 10–21.
10–34
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008