EP2C8T144C8N Datasheet, PDF (436/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Operation Control
Figure 14–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
Capture Phase
In the capture phase, the
0
signals at the pin, OEJ and
1
OUTJ, are loaded into the
capture registers. The CLOCK
signals are supplied by the
TAP controller’s CLOCKDR
OEJ
0
output. The data retained in
1
these registers consists of
signals from normal device
operation.
OUTJ
0
1
SDO
DQ
0
DQ
1
INJ
DQ
0
DQ
1
DQ
0
DQ
1
Shift & Update Phases
Capture
Registers
Update
Registers
In the shift phase, the
previously captured signals at
the pin, OEJ and OUTJ, are
shifted out of the boundary-
scan register via the TDO pin
using CLOCK. As data is
shifted out, the patterns for
the next test can be shifted in
via the TDI pin.
SDI
SHIFT
CLOCK
UPDATE
SDO
0
1
DQ
DQ
In the update phase, data is
OEJ
transferred from the capture
0
to the UPDATE registers using
1
the UPDATE clock. The data
stored in the UPDATE
registers can be used for the
OUTJ
EXTEST instruction.
0
1
DQ
DQ
DQ
DQ
MODE
0
INJ
1
0
1
0
1
Capture
Registers
Update
Registers
SDI
SHIFT
CLOCK
UPDATE
MODE
14–10
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007