EP2C8T144C8N Datasheet, PDF (256/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interface Standards
External
Memory
Interface
Standards
The following sections describe how to use Cyclone II device external
memory interfacing features.
DDR & DDR2 SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed. These devices transfer data on both the rising
and falling edge of the clock signal. DDR2 SDRAM is the second
generation memory based on the DDR SDRAM architecture and is
capable of data transfer rates of up to 533 Mbps. Cyclone II devices
support DDR and DDR2 SDRAM at up to 333 Mbps.
Interface Pins
DDR and DDR2 SDRAM devices use interface pins such as data (DQ),
data strobe (DQS), clock, command, and address pins to communicate
with the memory controller. Data is sent and captured at twice the system
clock rate by transferring data on the positive and negative edge of the
clock. The commands and addresses use only one active (positive) edge
of a clock.
DDR SDRAM uses single-ended data strobe DQS, while DDR2 SDRAM
has the option to use differential data strobes DQS and DQS#. Cyclone II
devices do not use the optional differential data strobes for DDR2
SDRAM interfaces. You can leave the DDR2 SDRAM memory DQS# pin
unconnected, because only the shifted DQS signal from the clock delay
control circuitry captures data. DDR and DDR2 SDRAM ×16 devices use
two DQS pins, and each DQS pin is associated with eight DQ pins.
However, this is not the same as the ×16/×18 mode in Cyclone II devices.
You need to configure the Cyclone II devices to use two sets of pins in ×8
mode. Similarly, if your ×72 memory module uses nine DQS pins where
each DQS pin is associated with eight DQ pins, configure the Cyclone II
device to use nine sets of DQS/DQ groups in ×8 mode.
Connect the memory device’s DQ and DQS pins to the Cyclone II DQ and
DQS pins, respectively, as listed in the Cyclone II pin tables. DDR and
DDR2 SDRAM also use active-high data mask (DM) pins for writes. DM
pins are pre-assigned in pin outs for Cyclone II devices, and these are the
preferred pins. However, you may connect the memory device’s DM pins
to any of the Cyclone II I/O pins in the same bank as the DQ pins of the
FPGA. There is one DM pin per DQS/DQ group. If the DDR or DDR2
SDRAM device supports ECC, the design uses an extra DQS/DQ group
for the ECC pins.
9–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007