EP2C8T144C8N Datasheet, PDF (384/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PS Configuration
PS Configuration Timing
A PS configuration must meet the setup and hold timing parameters and
the maximum clock frequency. When using a microprocessor or another
intelligent host to control the PS interface, ensure that you meet these
timing requirements.
Figure 13–12 shows the timing waveform for PS configuration for
Cyclone II devices.
Figure 13–12. PS Configuration Timing Waveform
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
Note (1)
nSTATUS (2)
CONF_DONE (3)
DCLK (4)
DATA
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Bit 0 Bit 1
t_DSU
Bit 2
Bit 3
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
Bit n
(5)
User Mode
t_CD2UM
Notes to Figure 13–12:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS and CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Cyclone II device holds nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more
convenient. When using the AS configuration scheme, DCLK is a Cyclone II output pin and should not be driven
externally.
(5) Do not leave the DATA pin floating after configuration. Drive it high or low, whichever is more convenient.
13–30
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007