EP2C8T144C8N Datasheet, PDF (32/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Logic Elements
Figure 2–4. LE in Arithmetic Mode
sload
sclear
(LAB Wide) (LAB Wide)
data1
data2
cin (from cout
of previous LE)
Register chain
connection
Three-Input
LUT
Three-Input
LUT
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
cout
Q
D
ENA
CLRN
Register Feedback
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register
chain output
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 LEs by
automatically linking LABs in the same column. For enhanced fitting, a
long carry chain runs vertically, which allows fast horizontal connections
to M4K memory blocks or embedded multipliers through direct link
interconnects. For example, if a design has a long carry chain in a LAB
column next to a column of M4K memory blocks, any LE output can feed
an adjacent M4K memory block through the direct link interconnect.
Whereas if the carry chains ran horizontally, any LAB not next to the
column of M4K memory blocks would use other row or column
interconnects to drive a M4K memory block. A carry chain continues as
far as a full column.
2–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007