EP2C8T144C8N Datasheet, PDF (290/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Supported I/O Standards
Figure 10–1. SSTL-2 Class I Termination
Output Buffer
25 Ω
V_TT = 1.25 V
Z = 50 Ω
50 Ω
V_REF = 1.25 V
Input Buffer
Figure 10–2. SSTL-2 Class II Termination
V_TT = 1.25 V
V_TT = 1.25 V
Output Buffer
50 Ω
50 Ω
25 Ω
Z = 50 Ω
V_REF = 1.25 V
Input Buffer
Cyclone II devices support both input and output SSTL-2 class I and II
levels.
Pseudo-Differential SSTL-2
The differential SSTL-2 I/O standard (EIA/JEDEC standard JESD8-9A) is
a 2.5-V standard used for applications such as high-speed DDR SDRAM
clock interfaces. This standard supports differential signals in systems
using the SSTL-2 standard and supplements the SSTL-2 standard for
differential clocks. The differential SSTL-2 standard specifies an input
voltage range of – 0.3 V ≤V_I ≤V_CCIO + 0.3 V. The differential SSTL-2
standard does not require an input reference voltage. Refer to
Figures 10–3 and 10–4 for details on differential SSTL-2 terminations.
Cyclone II devices do not support true differential SSTL-2 standards.
Cyclone II devices support pseudo-differential SSTL-2 outputs for
PLL_OUT pins and pseudo-differential SSTL-2 inputs for clock pins.
Pseudo-differential inputs require an input reference voltage as opposed
to the true differential inputs. Refer to Table 10–1 on page 10–2 for
information about pseudo-differential SSTL.
10–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008