EP2C8T144C8N Datasheet, PDF (422/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Device Configuration Pins
Table 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 5 of 5)
Pin Name
DCLK
User Configuration
Mode Scheme
Pin Type
N/A PS,
AS
Input (PS)
Output (AS)
Description
In PS configuration, DCLK is the clock input used to
clock data from an external source into the target
device. Data is latched into the Cyclone II device on
the rising edge of DCLK.
In AS mode, DCLK is an output from the Cyclone II
device that provides timing for the configuration
interface. In AS mode, DCLK has an internal pull-up
that is always active.
After configuration, this pin is tri-stated. If you are
using a configuration device, it drives DCLK low after
configuration is complete. If your design uses a
control host, drive DCLK either high or low. Toggling
this pin after configuration does not affect the
configured device.
DATA0
N/A All
Input
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
This is the data input pin. In serial configuration
modes, bit-wide configuration data is presented to the
target device on the DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor
that is always active.
After configuration, EPC1 and EPC1441 devices
tri-state this pin, while enhanced configuration and
EPC2 devices drive this pin high.
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
13–68
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007