XC3SD3400A-4FGG676C Datasheet, PDF(98/101 Page) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

XC3SD3400A-4FGG676C Datasheet, PDF (98/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

◁

Spartan-3A DSP FPGA Family: Pinout Descriptions

14

I/O

L26N_0

GCLK7

I/O

L26P_0

GCLK6

GND

15

16

17

I/O

GND INPUT

L23N_0

I/O VCCO_0 I/O

L23P_0

L19N_0

I/O

I/O

I/O

L22N_0 L21N_0 L19P_0

Bank 0

18

19

I/O

I/O

L18N_0 L15N_0

I/O

I/O

L18P_0 L15P_0

I/O

GND

L17N_0

20

I/O

L14N_0

I/O

L14P_0

VREF_0

I/O

L11N_0

21

GND

22

I/O

L07N_0

23 24 25

GND VCCAUX

â

â

TCK

I/O VCCO_0 I/O

L09N_0

L07P_0

GND

â

GND

â

I/O

I/O

I/O

L09P_0 L05N_0 L06N_0

GND

I/O

L63N_1

A23

26

GND A

INPUT

VREF_1 B

â

I/O

L63P_1 C

A22

INPUT

VREF_0

GND

â

I/O

I/O

I/O

L22P_0 L21P_0 L17P_0

GND

â

I/O

L11P_0

I/O

L10N_0

I/O

L05P_0

I/O

L06P_0

I/O

L61N_1

I/O

L61P_1

I/O

L60N_1

D

I/O

L24P_0

I/O

L20N_0 VCCAUX

VREF_0

I/O

L13N_0

â VCCAUX

INPUT VCCO_0

I/O

VCCAUX

L10P_0

TDO

I/O

L56P_1

VCCO_1

I/O

L60P_1

E

I/O

L24N_0

INPUT

GND

I/O

L25N_0

GCLK5

I/O

L20P_0

I/O

L16P_0

I/O

L16N_0

INPUT

GND

I/O VCCINT I/O

L13P_0

â

L02N_0

GND

â

I/O VCCINT I/O

L08N_0

â

L02P_0

VREF_0

VCCO_0 I/O INPUT GND

L08P_0

I/O INPUT VCCAUX I/O

L12P_0 VREF_0

L59P_1

I/O

L01N_0

I/O

L01P_0

I/O

L64P_1

A24

I/O

L59N_1

GND

I/O

L58P_1

VREF_1

I/O

L56N_1

I/O

L54N_1

I/O

L64N_1

A25

I/O

L58N_1

I/O

L51P_1

I/O

L51N_1

I/O

VCCAUX INPUT

L62N_1 VCCO_1

A21

â

â

I/O

L62P_1

A20

I/O

L49N_1

I/O

L49P_1

GND

I/O

L54P_1

GND

F

INPUT VCCAUX

VREF_1

â

â

G

VCCO_1 INPUT

â

VREF_1 H

â

I/O

I/O

L43N_1 L43P_1 J

A19

A18

I/O

L25P_0

GCLK4

VCCINT

I/O

L12N_0

GND

I/O

L57N_1

I/O

L57P_1

I/O

L53N_1

I/O

L50N_1

I/O

L46N_1

I/O

L46P_1

INPUT

L40P_1

I/O

L41P_1

I/O

L41N_1

K

VCCINT GND VCCINT I/O

I/O VCCO_1 I/O

L55N_1 L55P_1

L53P_1

GND

I/O

L50P_1

INPUT

L40N_1

I/O

L38P_1

A12

VCCO_1

GND

L

GND

VCCINT

GND

VCCINT I/O

L47N_1

I/O

L47P_1

I/O

L42N_1

A17

I/O

L45P_1

I/O

L45N_1

I/O

L38N_1

A13

INPUT

L36P_1

VREF_1

I/O

L35N_1

A11

I/O

L35P_1 M

A10

VCCINT

GND

I/O

VCCINT L39N_1

A15

I/O

L39P_1

A14

I/O

L34N_1

RHCLK7

I/O

L42P_1

A16

I/O

L37N_1

VCCO_1

INPUT

L36N_1

I/O

L33N_1

RHCLK5

INPUT

L32N_1

INPUT

L32P_1

N

VCCINT VCCINT GND

VCCAUX

I/O

L34P_1

IRDY1

RHCLK6

GND

I/O

I/O

L30N_1 L30P_1

RHCLK1 RHCLK0

I/O

L37P_1

I/O

L33P_1

RHCLK4

GND

I/O

I/O

L31N_1

TRDY1

L31P_1

RHCLK2

P

RHCLK3

VCCINT

GND

I/O

VCCINT L27N_1

A7

I/O

L27P_1

A6

I/O

L22P_1

I/O

L22N_1

I/O

L25P_1

A2

I/O

L25N_1

A3

INPUT

L28P_1

VREF_1

INPUT

L28N_1

I/O

L29P_1

A8

I/O

L29N_1 R

A9

GND VCCINT GND

VCCAUX I/O

I/O

L35N_2 L42N_2

I/O

I/O

I/O

L31P_2 L35P_2 L42P_2

I/O

L17N_1

GND

I/O

L46N_2

I/O

L17P_1

I/O

L12N_1

I/O

L08P_1

VCCO_1 I/O

L14N_1

I/O

I/O

L12P_1 L10N_1

I/O SUSPEN

L08N_1

D

GND

I/O

L14P_1

I/O

L10P_1

VCCAUX

I/O

L26P_1

A4

I/O

I/O

L21N_1 L23P_1

I/O

I/O

L18N_1 L21P_1

I/O

L26N_1

A5

I/O

L23N_1

VREF_1

I/O

L19P_1

VCCO_1 GND T

GND

â

I/O

L19N_1

INPUT

VREF_1 U

â

INPUT

VREF_1 V

â

GND

â I/O

VCCO_2

I/O

VCCINT

GND

L31N_2

L46P_2

I/O

I/O VCCO_1 I/O

L04P_1 L04N_1

L18P_1

GND

GND VCCAUX

â âW

I/O

L27P_2

GCLK0

I/O

L34N_2

D3

INPUT

VREF_2

I/O VCCINT VCCINT I/O

L43N_2

â

â

L01P_1

HDC

I/O

L01N_1

LDC2

I/O

L13P_1

I/O

L13N_1

I/O

L15P_1

I/O

L15N_1

INPUT

â

Y

I/O

L27N_2

GCLK1

I/O

L34P_2

INIT_B

GND

I/O

I/O

L43P_2 L47N_2

GND

â

INPUT

VREF_2

GND

I/O

I/O

I/O

I/O

L09P_1 L09N_1 L11P_1 L11N_1

GND

A

A

VCCO_2

I/O

L30N_2

MOSI

CSI_B

â I/O

VCCAUX

I/O

VCCO_2

L38N_2

L47P_2

GND

â

DONE

VCCAUX

I/O

L07P_1

I/O

L07N_1 VCCO_1

VREF_1

I/O

L06N_1

A

B

I/O

I/O

I/O INPUT

L29N_2 L30P_2 L38P_2

GND

â

I/O

I/O

I/O

L40N_2 L41N_2 L45N_2

I/O

2

I/O

I/O

I/O

I/O A

L03P_1

A0

L03N_1

A1

L05N_1

L06P_1

C

I/O

L29P_2

I/O

L32P_2

AWAKE

INPUT

I/O

L33N_2

GND

I/O

I/O

I/O

I/O

L40P_2 L41P_2 L44N_2 L45P_2

GND

â

GND

I/O

I/O A

L02N_1

LDC0

L05P_1

D

I/O

L28N_2

GCLK3

I/O

L32N_2

DOUT

VCCO_2

I/O

L33P_2

I/O

L36N_2

D1

I/O

L37N_2

I/O

L39N_2

I/O VCCO_2 I/O

L44P_2

L48N_2

I/O

L52N_2

CCLK

I/O

L51N_2

I/O A

L02P_1

LDC1

E

I/O

L28P_2

GCLK2

INPUT

VREF_2

GND

INPUT

VREF_2

I/O

L36P_2

D2

I/O

L37P_2

I/O

L39P_2

GND

INPUT

VREF_2

I/O

L48P_2

I/O

L52P_2

D0

DIN/MISO

I/O

L51P_2

A

GND

F

Bank 2

Right Half of FG676

Package (Top View)

Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top ViewâRight Half)

DS610 (v3.0) October 4, 2010

www.xilinx.com

Product Specification

98

▷