XC3SD3400A-4FGG676C Datasheet, PDF (43/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 35: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A
Speed Grade
Symbol
Description
Pre-adder Multiplier Post-adder
-5
-4
Units
Max
Max
Clock to Out from Output Register Clock to Output Pin
T_{DSPCKO_PP}
CLK (PREG) to P output
–
–
–
1.26
1.44
ns
Clock to Out from Pipeline Register Clock to Output Pins
T_{DSPCKO_PM}
CLK (MREG) to P output
–
Yes
Yes
3.16
3.63
ns
–
Yes
No
1.94
2.23
ns
Clock to Out from Input Register Clock to Output Pins
T_{DSPCKO_PA}
CLK (AREG) to P output
–
Yes
Yes
6.33
7.27
ns
T_{DSPCKO_PB}
CLK (BREG) to P output
Yes
Yes
Yes
7.45
8.56
ns
T_{DSPCKO_PC}
CLK (CREG) to P output
–
–
Yes
3.37
3.87
ns
T_{DSPCKO_PD}
CLK (DREG) to P output
Yes
Yes
Yes
7.33
8.42
ns
Combinatorial Delays from Input Pins to Output Pins
T_{DSPDO_AP}
T_{DSPDO_BP}
A or B input to P output
–
No
Yes
2.78
3.19
ns
–
Yes
No
4.60
5.28
ns
–
Yes
Yes
5.65
6.49
ns
T_{DSPDO_BP}
B input to P output
Yes
No
Yes
Yes
No
3.49
4.01
ns
No
5.79
6.65
ns
Yes
Yes
Yes
6.74
7.74
ns
T_{DSPDO_CP}
C input to P output
T_{DSPDO_DP}
D input to P output
T_{DSPDO_OPP}
OPMODE input to P output
Maximum Frequency
–
–
Yes
2.76
3.17
ns
Yes
Yes
Yes
6.81
7.82
ns
Yes
Yes
Yes
7.12
8.18
ns
F_MAX
All registers used
Yes
Yes
Yes
287
250
MHz
Notes:
1. To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.
2. "Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not
applicable.
3. The numbers in this table are based on the operating conditions set forth in Table 7.
DS610 (v3.0) October 4, 2010
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Product Specification
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