XC3SD3400A-4FGG676C Datasheet, PDF (96/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 69 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
AWAKE pin is counted as a dual-purpose I/O.
Table 69: User I/Os Per Bank for the XC3SD3400A in the FG676 Package
Package
Edge
I/O Bank
Maximum I/Os
and
Input-Only
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF⁽¹⁾
Top
0
111
82
11
1
9
Right
1
123
67
8
30
10
Bottom
2
112
68
6
21
9
Left
3
123
97
9
0
9
TOTAL
469
314
34
52
37
CLK
8
8
8
8
32
Notes:
1. 26 VREF are on INPUT pins.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
96