XC3SD3400A-4FGG676C Datasheet, PDF (56/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
X-Ref Target - Figure 13
PROG_B
(Input)
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
VS[2:0]
(Input)
M[2:0]
(Input)
INIT_B
(Open-Drain)
<1:1:1>
T_MINIT
<0:0:1>
T_INITM
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
New ConfigRate active
CCLK
T_CCLK1
T_MCCL1 T_MCCH1
T_MCCLn
T_CCLK1
T_CCLKn
T_MCCHn
DIN
(Input)
CSO_B
MOSI
T_V
T_CSS
Data
Data
T_DCC
Data
Data
T_CCD
T_CCO
Command
(msb)
Command
(msb-1)
T_DSU
T_DH
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
Shaded values indicate specifications on attached SPI Flash PROM.
Figure 13: Waveforms for Serial Peripheral Interface (SPI) Configuration
DS529-3_06_102506
Table 52: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
T_INITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
T_CCO
T_DCC
T_CCD
MOSI output valid delay after CCLK falling edge
Setup time on DIN data input before CCLK rising edge
Hold time on DIN data input after CCLK rising edge
Minimum
50
Maximum
See Table 46
See Table 46
–
0
–
See Table 50
See Table 50
See Table 50
Units
ns
ns
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
56