XC3SD3400A-4FGG676C Datasheet, PDF (27/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Output Propagation Times
Table 23: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
Clock-to-Output Times
T_IOCKP
When reading from the Output
LVCMOS25⁽²⁾, 12 mA output
All
Flip-Flop (OFF), the time from the
drive, Fast slew rate
active transition at the OCLK input to
data appearing at the Output pin
Propagation Times
T_IOOP
The time it takes for data to travel from LVCMOS25⁽²⁾, 12 mA output
All
the IOB’s O input to the Output pin drive, Fast slew rate
Set/Reset Times
T_IOSRP
Time from asserting the OFF’s SR
LVCMOS25⁽²⁾, 12 mA output
All
input to setting/resetting data at the drive, Fast slew rate
Output pin
T_IOGSRQ
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Speed Grade
-5
-4
Max Max
Units
2.87
3.13
ns
2.78
2.91
ns
3.63
3.89
ns
8.62
9.65
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 25.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
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