XC3SD3400A-4FGG676C Datasheet, PDF (11/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
General Recommended Operating Conditions
Table 7: General Recommended Operating Conditions
Symbol
Description
Min
Nominal
Max
Units
T_J
Junction temperature
Commercial
Industrial
0
–
–40
–
85
°C
100
°C
V_CCINT
V_CCO ⁽¹⁾
V_CCAUX
V_IN(3)
T_IN
Internal supply voltage
Output driver supply voltage
Auxiliary supply voltage⁽²⁾ V_CCAUX = 2.5
V_CCAUX = 3.3
Input voltage
PCI™ IOSTANDARD
All other
IOSTANDARDs
IP or IO_#
IO_Lxxy_#⁽⁴⁾
Input signal transition time⁽⁵⁾
1.14
1.10
2.25
3.00
–0.5
–0.5
–0.5
–
1.20
1.26
V
–
3.60
V
2.50
2.75
V
3.30
3.60
V
–
V_CCO+0.5
V
–
4.10
V
–
4.10
V
–
500
ns
Notes:
1. This V_CCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 10 lists the recommended V_CCO
range specific to each of the single-ended I/O standards, and Table 12 lists that specific to the differential standards.
2. Define V_CCAUX selection using CONFIG VCCAUX constraint.
3. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.
4. For single-ended signals that are placed on a differential-capable I/O, V_IN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
5. Measured between 10% and 90% V_CCO. Follow Signal Integrity recommendations.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
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