XC3SD3400A-4FGG676C Datasheet, PDF (55/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Slave Parallel Mode Timing
X-Ref Target - Figure 12
PROG_B
(Input)
INIT_B
(Open-Drain)
CSI_B
(Input)
RDWR_B
(Input)
CCLK
(Input)
T_SMCCW
T_SMCSCC
T_SMDCC
T_SMCCD
T_SMCCCS
T_MCCH
T_SCCH
T_MCCL
T_SCCL
1/F_CCPAR
T_SMWCC
D0 - D7
(Inputs)
Notes:
Byte 0
Byte 1
Byte n
Byte n+1
DS529-3_02_051607
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332, Chapter 7, section “Non-Continuous SelectMAP Data
Loading” for more details.
Figure 12: Waveforms for Slave Parallel Configuration
Table 51: Timing for the Slave Parallel Configuration Mode
Symbol
Description
All Speed Grades
Min
Max
Setup Times
T_SMDCC(2)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
7
–
T_SMCSCC
Setup time on the CSI_B pin before the rising transition at the CCLK pin
7
–
T_SMCCW
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
17
–
Hold Times
T_SMCCD
The time from the rising transition at the CCLK pin to the point when data is last held at
1
–
the D0-D7 pins
T_SMCCCS
The time from the rising transition at the CCLK pin to the point when a logic level is last
0
–
held at the CSO_B pin
T_SMWCC
The time from the rising transition at the CCLK pin to the point when a logic level is last
0
–
held at the RDWR_B pin
Clock Timing
T_CCH
T_CCL
F_CCPAR
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal at the CCLK input pin No bitstream compression
With bitstream compression
5
–
5
–
0
80
0
80
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7.
2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
Units
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
55