XC3SD3400A-4FGG676C Datasheet, PDF (72/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 64 and Table 65 indicates how the user-I/O pins are distributed between the four I/O banks on the CS484 package.
The AWAKE pin is counted as a dual-purpose I/O.
Table 64: User I/Os Per Bank for the XC3SD1800A in the CS484 Package
Package
Edge
I/O Bank
Maximum I/Os
and
Input-Only
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF⁽¹⁾
Top
0
77
49
13
1
6
Right
1
78
23
9
30
8
Bottom
2
76
33
6
21
8
Left
3
78
51
13
0
6
TOTAL
309
156
41
52
28
CLK
8
8
8
8
32
Notes:
1. 19 VREF are on INPUT pins.
Table 65: User I/Os Per Bank for the XC3SD3400A in the CS484 Package
Package
Edge
I/O Bank
Maximum I/O
and
Input-Only
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF⁽¹⁾
Top
0
77
49
13
1
6
Right
1
78
23
9
30
8
Bottom
2
76
33
6
21
8
Left
3
78
51
13
0
6
TOTAL
309
156
41
52
28
CLK
8
8
8
8
32
Notes:
1. 19 VREF are on INPUT pins.
Footprint Migration Differences
There are no migration footprint differences between the XC3SD1800A and the XC3SD3400A in the CS484 package.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
72