XC3SD3400A-4FGG676C Datasheet, PDF (41/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Block RAM Timing
Table 33: Block RAM Timing
Symbol
Description
Clock-to-Output Times
T_{RCKO_DOA_NC} When reading from block RAM, the delay from the active transition at
the CLK input to data appearing at the DOUT output
T_{RCKO_DOA}
Clock CLK to DOUT output (with output register)
Setup Times
T_{RCCK_ADDR} Setup time for the ADDR inputs before the active transition at the CLK
input of the block RAM
T_{RDCK_DIB}
Setup time for data at the DIN inputs before the active transition at the
CLK input of the block RAM
T_{RCCK_ENB}
Setup time for the EN input before the active transition at the CLK input
of the block RAM
T_{RCCK_WEB}
Setup time for the WE input before the active transition at the CLK input
of the block RAM
T_{RCCK_REGCE} Setup time for the CE input before the active transition at the CLK input
of the block RAM
T_{RCCK_RST}
Setup time for the RST input before the active transition at the CLK
input of the block RAM
Hold Times
T_{RCKC_ADDR} Hold time on the ADDR inputs after the active transition at the CLK
input
T_{RCKC_DIB}
T_{RCKC_ENB}
T_{RCKC_WEB}
T_{RCKC_REGCE}
T_{RCKC_RST}
Clock Timing
Hold time on the DIN inputs after the active transition at the CLK input
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
Hold time on the CE input after the active transition at the CLK input
Hold time on the RST input after the active transition at the CLK input
T_BPWH
High pulse width of the CLK signal
T_BPWL
Low pulse width of the CLK signal
Clock Frequency
F_BRAM
Block RAM clock frequency
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7.
Speed Grade
-5
-4
Min Max Min Max
–
2.38
–
2.80
–
1.24
–
1.45
0.40
–
0.46
–
0.29
–
0.33
–
0.51
–
0.60
–
0.64
–
0.75
–
0.34
–
0.40
–
0.22
–
0.25
–
0.09
–
0.10
–
0.09
–
0.10
–
0.09
–
0.10
–
0.09
–
0.10
–
0.09
–
0.10
–
0.09
–
0.10
–
1.56
–
1.79
–
1.56
–
1.79
–
0
320
0
280
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
41