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XC3SD3400A-4FGG676C Datasheet, PDF (12/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol
Description
IL(2) Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Test Conditions
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
Min Typ Max Units
–10 – +10 µA
IHS Leakage current on pins during All pins except INIT_B, PROG_B, DONE, and JTAG pins –10
–
+10 µA
hot socketing, FPGA unpowered when PUDC_B = 1.
INIT_B, PROG_B, DONE, and JTAG pins or other pins
when PUDC_B = 0.
Add IHS + IRPU
µA
IRPU(3)
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.
VIN = GND
VCCO or VCCAUX = 3.0V to 3.6V –151 –315 –710 µA
VCCO or VCCAUX = 2.3V to 2.7V –82 –182 –437 µA
VCCO = 1.7V to 1.9V
–36 –88 –226 µA
VCCO = 1.4V to 1.6V
–22 –56 –148 µA
RPU(3)
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 2)
VIN = GND
VCCO = 1.14V to 1.26V
VCCO = 3.0V to 3.6V
VCCO = 2.3V to 2.7V
VCCO = 1.7V to 1.9V
–11 –31 –83 µA
5.1 11.4 23.9 kΩ
6.2 14.8 33.1 kΩ
8.4 21.6 52.6 kΩ
VCCO = 1.4V to 1.6V
10.8 28.4 74.0 kΩ
IRPD(3)
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
VIN = VCCO
VCCO = 1.14V to 1.26V
VCCAUX = 3.0V to 3.6V
VCCAUX = 2.25V to 2.75V
15.3 41.1 119.4 kΩ
167 346 659 µA
100 225 457 µA
RPD(3)
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 2)
VCCAUX = 3.0V to 3.6V
VIN = 3.0V to 3.6V
VIN = 2.3V to 2.7V
VIN = 1.7V to 1.9V
5.5 10.4 20.8 kΩ
4.1 7.8 15.7 kΩ
3.0 5.7 11.1 kΩ
VIN = 1.4V to 1.6V
2.7 5.1 9.6 kΩ
VIN = 1.14V to 1.26V
2.4 4.5 8.1 kΩ
VCCAUX = 2.25V to 2.75V
VIN = 3.0V to 3.6V
7.9 16.0 35.0 kΩ
VIN = 2.3V to 2.7V
VIN = 1.7V to 1.9V
5.9 12.0 26.3 kΩ
4.2 8.5 18.6 kΩ
VIN = 1.4V to 1.6V
3.6 7.2 15.7 kΩ
VIN = 1.14V to 1.26V
3.0 6.0 12.5 kΩ
IREF VREF current per pin
All VCCO levels
–10 – +10 µA
CIN Input capacitance
–
–
–
10 pF
RDT Resistance of optional
differential termination circuit
within a differential I/O pair. Not
available on Input-only pairs.
VCCO = 3.3V ± 10%
VCCO = 2.5V ± 10%
LVDS_33, MINI_LVDS_33,
RSDS_33
LVDS_25, MINI_LVDS_25,
RSDS_25
90 100 115 Ω
90 110 –
Ω
Notes:
1. The numbers in this table are based on the conditions set forth in Table 7.
2. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
3. This parameter is based on characterization. The pull-up resistance RPU = VCCO/IRPU. The pull-down resistance RPD = VIN / IRPD.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
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