XC3SD3400A-4FGG676C Datasheet, PDF (100/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: Pinout Descriptions
Table 70: FG676 Footprint Migration Differences (Cont’d)
FG676
Ball
Spartan-3A
XC3S1400A
Type
XC3S1400A
Bank
Spartan-3A DSP
XC3SD1800A XC3SD1800A
Type
Bank
Y8
N.C.
N.C.
IP_2
2
Y11
IP_2
2
IP_2
2
Y18
N.C.
N.C.
IP_2
2
Y19
N.C.
N.C.
IP_2/VREF_2
2
W18
N.C.
N.C.
IP_2
2
AF2
IP_2
2
IP_2
2
AF7
IP_2
2
IP_2
2
AD5
N.C.
N.C.
IP_2
2
AD23
N.C.
N.C.
IP_2
2
AC5
N.C.
N.C.
IP_2
2
AC7
IP_2
2
IP_2
2
AC18
IP_2
2
IP_2
2
AB10 IP_2/VREF_2
2
IP_2/VREF_2
2
AB17
IP_2
2
IP_2
2
AB20
IP_2
2
IP_2
2
AA8
N.C.
N.C.
IP_2
2
AA19
IP_2
2
IP_2
2
AC22
N.C.
N.C.
IO_2
2
Y3
IP_L54P_3
3
IP_L54P_3
3
Y4
IP_L54N_3
3
IP_L54N_3
3
H4
IP_L12N_3/
3
IP_L12N_3/
3
VREF_3
VREF_3
G1
IP_L16N_3
3
IP_L16N_3
3
G2
IP_L16P_3
3
IP_L16P_3
3
G5
IP_L12P_3
3
IP_L12P_3
3
D1
IP_L08N_3
3
IP_L08N_3
3
D2
IP_L08P_3
3
IP_L08P_3
3
C1
IP_L04N_3/
3
IP_L04N_3/
3
VREF_3
VREF_3
C2
IP_L04P_3
3
IP_L04P_3
3
AB3
IP_L62P_3
3
IP_L62P_3
3
AB4
IP_L62N_3
3
IP_L62N_3
3
AA4
IP_L58P_3
3
IP_L58P_3
3
AA5
IP_L58N_3/
3
IP_L58N_3/
3
VREF_3
VREF_3
Spartan-3A DSP
XC3SD3400A XC3SD3400A
Type
Bank
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCO_2
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
GND
GND
VCCINT
VCCINT
GND
GND
IO_2
2
IP_3
3
VCCINT
VCCINT
IP_3/VREF_3
3
IP_3
GND
GND
VCCAUX
GND
IP_3/VREF_3
3
GND
GND
VCCAUX
GND
3
VCCO_3
GND
VCCAUX
GND
IP_3/VREF_3
3
GND
VCCAUX
GND
3
FG676
Ball
Y8
Y11
Y18
Y19
W18
AF2
AF7
AD5
AD23
AC5
AC7
AC18
AB10
AB17
AB20
AA8
AA19
AC22
Y3
Y4
H4
G1
G2
G5
D1
D2
C1
C2
AB3
AB4
AA4
AA5
Migration Recommendations
There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package.
Please note the differences between the two devices from Table 70 and take the necessary precautions.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
100