XC3SD3400A-4FGG676C Datasheet, PDF (25/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 21: Propagation Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
DELAY_VALUE
T_IOPLI The time it takes for data to travel from LVCMOS25⁽²⁾
0
the Input pin through the IFF latch to the
I output with no input delay programmed
T_IOPLID The time it takes for data to travel from LVCMOS25⁽²⁾
1
the Input pin through the IFF latch to the
I output with the input delay programmed
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Device
Speed
Grade
-5 -4
Units
Max Max
XC3SD1800A 1.79 2.04 ns
XC3SD3400A 1.65 2.11 ns
XC3SD1800A 2.23 2.47 ns
2.81 3.06 ns
3.39 3.86 ns
3.89 4.43 ns
3.83 4.39 ns
4.61 5.32 ns
5.40 6.24 ns
5.93 6.86 ns
XC3SD3400A 2.21 2.67 ns
2.71 3.25 ns
3.58 4.04 ns
4.15 4.62 ns
4.03 4.49 ns
4.57 5.31 ns
5.34 6.18 ns
5.84 6.78 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 22.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
25