XC3SD3400A-4FGG676C Datasheet, PDF (40/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
Symbol
Description
Minimum
T_GIO
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
–
T_GSI
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
–
F_BUFG
Frequency of signals distributed on global buffers (all sides)
0
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7.
Maximum
Speed Grade
-5
-4
0.22
0.23
0.56
0.63
350
334
Units
ns
ns
MHz
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
40