XC3SD3400A-4FGG676C Datasheet, PDF (28/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Three-State Output Propagation Times
Table 24: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Synchronous Output Enable/Disable Times
T_IOCKHZ
Time from the active transition at the OTCLK LVCMOS25, 12 mA
input of the Three-state Flip-Flop (TFF) to when output drive, Fast slew
the Output pin enters the high-impedance state rate
T_IOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Asynchronous Output Enable/Disable Times
T_GTS
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
Set/Reset Times
T_IOSRHZ
T_IOSRON(2)
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
LVCMOS25, 12 mA
output drive, Fast slew
rate
Device
All
All
All
All
All
Speed Grade
-5
-4
Max Max
Units
1.13 1.39
ns
3.08 3.35
ns
9.47 10.36 ns
1.61 1.86
ns
3.57 3.82
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 25.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
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