XC3SD3400A-4FGG676C Datasheet, PDF (23/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 19: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
T_IOICKPD
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF) to
the point where data must be held at the
Input pin. The Input Delay is
programmed.
LVCMOS25⁽³⁾
Set/Reset Pulse Width
T_{RPW_IOB} Minimum pulse width to SR control input
–
on IOB
DELAY_
VALUE
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
–
Device
Speed
-5 -4 _Units
Min Min
XC3SD1800A –1.40 –1.40 ns
–2.11 –2.11 ns
–2.48 –2.48 ns
–2.77 –2.77 ns
–2.62 –2.62 ns
–3.06 –3.06 ns
–3.42 –3.42 ns
–3.65 –3.65 ns
XC3SD3400A –1.31 –1.31 ns
–1.88 –1.88 ns
–2.44 –2.44 ns
–2.89 –2.89 ns
–2.83 –2.83 ns
–3.33 –3.33 ns
–3.63 –3.63 ns
–3.96 –3.96 ns
All
1.33 1.61 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 22.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 20: Sample Window (Source Synchronous)
Symbol Description
Max
T_SAMP
Setup and hold
capture window of
an IOB flip-flop.
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record 30879
Units
ps
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
23