XC3SD3400A-4FGG676C Datasheet, PDF(73/101 Page) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

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XC3SD3400A-4FGG676C Datasheet, PDF (73/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

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CS484 Footprint

Left Half of Package

(Top View)

I/O: Unrestricted,

156 general-purpose user I/O.

INPUT: Unrestricted,

41 general-purpose input pin.

DUAL: Configuration

51 pins, then possible user

I/O.

VREF: User I/O or input

28 voltage reference for bank.

CLK: User I/O, input, or

32 clock buffer input.

CONFIG: Dedicated

2 configuration pins.

SUSPEND: Dedicated

2 SUSPEND and

dual-purpose AWAKE

Power Management pins.

JTAG: Dedicated JTAG

4 port pins.

GND: Ground.

84

VCCO: Output voltage

24 supply for bank.

VCCINT: Internal core

36 supply voltage (+1.2V).

VCCAUX: Auxiliary

24 supply voltage

Spartan-3A DSP FPGA Family: Pinout Descriptions

Bank 0

1

2

3

4

5

6

7

8

9

10

11

A

GND

PROG_ I/O

B

L30N_0

I/O

L28N_0

I/O

L25N_0

I/O

L25P_0

I/O

I/O

L24N_0 L20P_0

VREF_0 GCLK10

I/O

L18P_0

GCLK6

INPUT

I/O

L15N_0

B

TMS VCCAUX I/O

I/O VCCO_0 I/O

L30P_0 L28P_0

L24P_0

GND

I/O

L20N_0

GCLK11

I/O

L18N_0

GCLK7

VCCO_0

I/O

L15P_0

C

I/O

L02N_3

I/O

L02P_3

GND

I/O

L29N_0

INPUT

I/O

L21P_0

I/O

L26P_0

I/O

L22P_0

I/O

L16P_0

INPUT

INPUT

0

VREF_0

D

INPUT

L04P_3

TDI

INPUT INPUT I/O

I/O

I/O

GND

I/O

I/O

GND

L08P_3 L08N_3 L29P_0 L21N_0 L26N_0

L22N_0 L16N_0

E

INPUT

L04N_3

VREF_3

VCCO_3

I/O

L09P_3

F

I/O

L06N_3

I/O

L06P_3

I/O

L01P_3

I/O VCCAUX INPUT

L09N_3

I/O

L31P_0

VREF_0

I/O

L27N_0

VCCO_0

INPUT

I/O

I/O

L03P_3 L03N_3

GND

I/O

L31N_0

PUDC_B

I/O

L27P_0

I/O

L23N_0

I/O

L19P_0

GCLK8

I/O

L19N_0

GCLK9

I/O

L17N_0

GCLK5

G

I/O

L11P_3

GND

I/O

L01N_3

GND

I/O

I/O VCCINT I/O

L07P_3 L07N_3

L23P_0

GND VCCAUX GND

H

I/O

L11N_3

I/O

L14P_3

I/O

L05P_3

I/O

L05N_3

I/O

L10P_3

I/O

L10N_3

GND

GND VCCINT GND VCCINT

J

I/O

L14N_3

VREF_3

VCCO_3

INPUT

L16P_3

INPUT VCCO_3 INPUT

L16N_3

L12P_3

INPUT

L12N_3 VCCINT

VREF_3

GND

VCCINT

GND

I/O

K L19P_3

LHCLK2

I/O

L17P_3

I/O

L17N_3

I/O

L13P_3

I/O

L13N_3

I/O VCCAUX

L15P_3

GND

VCCINT

GND

VCCINT

I/O

L L19N_3

IRDY2

LHCLK3

GND

I/O

L20P_3 VCCAUX

LHCLK4

I/O

L15N_3

I/O

L18P_3

LHCLK0

GND VCCINT GND VCCINT GND

M

I/O

L22P_3

VREF_3

I/O

L20N_3

LHCLK5

INPUT

L23P_3

GND

I/O

L18N_3

LHCLK1

I/O

L21P_3

TRDY2

LHCLK6

VCCAUX

GND

VCCINT

GND

VCCINT

N

I/O VCCO_3 INPUT

L22N_3

L31P_3

INPUT

L23N_3

I/O

L24N_3

I/O

L24P_3

I/O

L21N_3 VCCINT

LHCLK7

GND

VCCINT

GND

P

I/O

L25P_3

I/O

L25N_3

INPUT

L31N_3

I/O

L32P_3 VCCO_3

VREF_3

I/O

L26P_3

VCCAUX

GND

VCCINT

GND

VCCINT

R

I/O

L28N_3

I/O

L28P_3

I/O

L34P_3

GND

I/O

I/O

L32N_3 L26N_3

GND VCCINT GND VCCINT GND

T

I/O

L30P_3

GND

INPUT I/O

I/O

I/O VCCINT GND VCCAUX GND VCCAUX

L27P_3 L34N_3 L29N_3 L29P_3

U

I/O

L30N_3

I/O

L33P_3

INPUT

L27N_3

V

I/O

L33N_3

VCCO_3

I/O

L36N_3

W

I/O

L35N_3

I/O

L37N_3

I/O

L37P_3

Y

I/O

L35P_3

INPUT

L39P_3

GND

A INPUT

I/O

L39N_3 VCCAUX L01P_2

A VREF_3

M1

A

INPUT I/O

GND

2

L01N_2

B

VREF_2 M0

I/O

I/O

GND

L38P_3 L38N_3

I/O

L36P_3

VCCAUX

I/O

L02P_2

M2

INPUT

2

VREF_2

I/O

L03P_2

I/O

L07N_2

VS2

I/O

L03N_2

I/O

L07P_2

RDWR_B

INPUT

I/O VCCO_2 INPUT

L04N_2

I/O

I/O

I/O

L04P_2 L05P_2 L05N_2

I/O

L02N_2

CSO_B

I/O

L11P_2

GND

INPUT

GND

I/O

L08P_2

I/O

L11N_2

I/O

L10N_2

I/O

L14N_2

D4

GND

I/O VCCO_2 I/O

L06N_2

L10P_2

I/O

L14P_2

D5

I/O

L06P_2

INPUT

2

VREF_2

INPUT

VCCAUX

I/O

L13P_2

I/O

L13N_2

I/O

I/O

L15N_2 L15P_2

GCLK13 GCLK12

I/O

L08N_2

VCCO_2

I/O

L12N_2

D6

GND

I/O

L09P_2

VS1

I/O

L09N_2

VS0

I/O

L12P_2

D7

INPUT

2

VREF_2

Bank 2

Figure 15: CS484 Package Footprint (Top ViewâLeft Half)

DS610 (v3.0) October 4, 2010

www.xilinx.com

Product Specification

73

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