XC3SD3400A-4FGG676C Datasheet, PDF (15/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 11: DC Characteristics of User I/Os Using
Single-Ended Standards
IOSTANDARD
Attribute
LVTTL⁽³⁾
2
Test
Conditions
I_OL I_OH
(mA) (mA)
2 –2
Logic Level
Characteristics
V_OL
Max (V)
V_OH
Min (V)
0.4
2.4
4
4 –4
6
6 –6
8
8 –8
12 12 –12
16 16 –16
24 24 –24
LVCMOS33⁽³⁾ 2
2 –2
0.4
V_CCO – 0.4
4
4 –4
6
6 –6
8
8 –8
12 12 –12
16 16 –16
24⁽⁵⁾ 24 –24
LVCMOS25⁽³⁾ 2
2 –2
0.4
V_CCO – 0.4
4
4 –4
6
6 –6
8
8 –8
12 12 –12
16⁽⁵⁾ 16 –16
24⁽⁵⁾ 24 –24
LVCMOS18⁽³⁾ 2
2 –2
0.4
V_CCO – 0.4
4
4 –4
6
6 –6
8
8 –8
12⁽⁵⁾ 12 –12
16⁽⁵⁾ 16 –16
LVCMOS15⁽³⁾ 2
2 –2
0.4
V_CCO – 0.4
4
4 –4
6
6 –6
8⁽⁵⁾
8
–8
12⁽⁵⁾ 12 –12
LVCMOS12⁽³⁾ 2
2 –2
4⁽⁵⁾
4
–4
0.4
V_CCO – 0.4
6⁽⁵⁾
6
–6
Table 11: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
IOSTANDARD
Attribute
PCI33_3⁽⁴⁾
PCI66_3⁽⁴⁾
HSTL_I ⁽⁵⁾
HSTL_III ⁽⁵⁾
HSTL_I_18
HSTL_II_18⁽⁵⁾
HSTL_III_18
SSTL18_I
SSTL18_II⁽⁵⁾
SSTL2_I
SSTL2_II⁽⁵⁾
SSTL3_I
SSTL3_II⁽⁵⁾
Test
Conditions
Logic Level
Characteristics
I_OL I_OH
V_OL
(mA) (mA) Max (V)
V_OH
Min (V)
1.5
1.5
8
24
8
16
24
6.7
13.4
8.1
16.2
8
16
–0.5
–0.5
–8
10% V_CCO
10% V_CCO
0.4
–8
0.4
–8
0.4
–16
0.4
–8
0.4
–6.7 V_TT – 0.475
–13.4 V_TT – 0.603
–8.1 V_TT – 0.61
–16.2 V_TT – 0.81
–8 V_TT – 0.6
–16 V_TT – 0.8
90% V_CCO
90% V_CCO
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_TT + 0.475
V_TT + 0.603
V_TT + 0.61
V_TT + 0.81
V_TT + 0.6
V_TT + 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 7 and Table 10.
2. Descriptions of the symbols used in this table are as follows:
I_OL—the output current condition under which VOL is tested
I_OH—the output current condition under which VOH is tested
V_OL— the output voltage that indicates a Low logic level
V_OH—the output voltage that indicates a High logic level
V_CCO—the supply voltage for output drivers
V_TT—the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same V_OL and V_OH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/products/
design_resources/conn_central/protocols/pci_pcix.htm. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
5. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the Using I/O
Resources chapter in UG331.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
15