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XC3SD3400A-4FGG676C Datasheet, PDF (46/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 37: Switching Characteristics for the DLL (Cont’d)
Symbol
Description
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged over all steps
Device
Speed Grade
-5
-4
Min Max Min Max
Units
All
15
35
15
35 ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7 and Table 36.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of ±[1% of CLKIN period + 150]. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps.
5. The typical delay step size is 23 ps.
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
Symbol
Description
Input Frequency Ranges(2)
FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
FCLKFX < 150 MHz
FCLKFX > 150 MHz
Speed Grade
-5
-4
Min Max Min Max
Units
0.2
333(5)
0.2
333(5) MHz
–
±300
–
±300 ps
–
±150
–
±150 ps
–
±1
–
±1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. The DCM specifications are guaranteed when both adjacent DCMs are locked.
5. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
46
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