XC3SD3400A-4FGG676C Datasheet, PDF (1/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

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Spartan-3A DSP FPGA Family Data Sheet
DS610 October 4, 2010
Module 1:
Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
• Introduction
• Features
• Architectural Overview
• Configuration Overview
• General I/O Capabilities
• Supported Packages and Package Marking
• Ordering Information
Module 2:
Functional Description
DS610 (v3.0) October 4, 2010
The functionality of the Spartan®-3A DSP FPGA family is
described in the following documents.
• UG331: Spartan-3 Generation FPGA User Guide
• Clocking Resources
• Digital Clock Managers (DCMs)
• Block RAM
• Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources
• Programmable Interconnect
• ISE® Software Design Tools and IP Cores
• Embedded Processing and Control Solutions
• Pin Types and Package Overview
• Package Drawings
• Powering FPGAs
• Power Management
• UG332: Spartan-3 Generation Configuration User Guide
• Configuration Overview
• Configuration Pins and Behavior
• Bitstream Sizes
• Detailed Descriptions by Mode
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
• ISE iMPACT Programming Examples
• MultiBoot Reconfiguration
• Design Authentication using Device DNA
Product Specification
• UG431: XtremeDSP™ DSP48A for Spartan-3A DSP
FPGAs User Guide
• DSP48A Slice Design Considerations
• DSP48A Architecture Highlights
- 18 x 18-Bit Multipliers
- 48-Bit Accumulator
- 18-bit Pre-Adder
• DSP48A Application Examples
Module 3:
DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• Switching Characteristics
• I/O Timing
• Configurable Logic Block (CLB) Timing
• Digital Clock Manager (DCM) Timing
• Block RAM Timing
• XtremeDSP Slice Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS610 (v3.0) October 4, 2010
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
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DS610 October 4, 2010
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Product Specification
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