XC3SD3400A-4FGG676C Datasheet, PDF (33/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 26: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Differential
V_REF (V)
Inputs
V_L (V)
V_H (V)
Outputs⁽²⁾
R_T (Ω)
V_T (V)
Inputs and
Outputs
V_M (V)
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
–
V_ICM – 0.125 V_ICM + 0.125
50
–
V_ICM – 0.125 V_ICM + 0.125
50
–
V_ICM – 0.125 V_ICM + 0.125
1M
–
V_ICM – 0.125 V_ICM + 0.125
50
–
V_ICM – 0.125 V_ICM + 0.125
50
–
V_ICM – 0.3
V_ICM + 0.3
N/A
–
V_ICM – 0.3
V_ICM + 0.3
N/A
–
V_ICM – 0.1
V_ICM + 0.1
50
–
V_ICM – 0.1
V_ICM + 0.1
50
–
V_ICM – 0.1
V_ICM + 0.1
50
–
V_ICM – 0.1
V_ICM + 0.1
50
–
V_ICM – 0.1
V_ICM + 0.1
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
–
V_ICM – 0.5
V_ICM + 0.5
50
1.2
1.2
0
1.2
1.2
N/A
N/A
1.2
1.2
3.3
0.8
0.8
0.9
0.9
1.8
0.9
0.9
0.9
0.9
1.25
1.25
1.5
1.5
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
Notes:
1. Descriptions of the relevant symbols are:
V_REF – The reference voltage for setting the input switching threshold
V_ICM – The common mode input voltage
V_M – Voltage of measurement point on signal transition
V_L – Low-level test voltage at Input pin
V_H – High-level test voltage at Input pin
R_T – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
V_T – Termination voltage
2. The load capacitance (C_L) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available and
has equivalent characteristics but no PCI-X IP is supported.
The capacitive load (C_L) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a C_L value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
33