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XC3SD3400A-4FGG676C Datasheet, PDF (16/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet
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Differential I/O Standards
Differential Input Pairs
X-Ref Target - Figure 3
Internal
Logic
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
VINP
P
Differential
VINN
N
I/O Pair Pins
VINN
VINP
50%
VID
VICM
GND level
VICM
=
Input
common
mode
voltage
=
VINP
+
2
VINN
VID = Differential input voltage = VINP - VINN
DS610-3_03_061507
Figure 3: Differential Input Voltages
Table 12: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1)
VID
Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V)
VICM(2)
Nom (V)
LVDS_25(3)
LVDS_33(3)
BLVDS_25(4)
MINI_LVDS_25(3)
MINI_LVDS_33(3)
LVPECL_25(5)
LVPECL_33(5)
RSDS_25(3)
RSDS_33(3)
TMDS_33(3,4,7)
PPDS_25(3)
PPDS_33(3)
2.25
2.5
2.75
100
350
600
0.3
1.25
3.0
3.3
3.6
100
350
600
0.3
1.25
2.25
2.5
2.75
100
300
–
0.3
1.3
2.25
2.5
2.75
200
–
600
0.3
1.2
3.0
3.3
3.6
200
–
600
0.3
1.2
Inputs Only
100
800
1000
0.3
1.2
Inputs Only
100
800
1000
0.3
1.2
2.25
2.5
2.75
100
200
–
0.3
1.2
3.0
3.3
3.6
100
200
–
0.3
1.2
3.14
3.3
3.47
150
–
1200
2.7
–
2.25
2.5
2.75
100
–
400
0.2
–
3.0
3.3
3.6
100
–
400
0.2
–
DIFF_HSTL_I_18
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–
1.7
1.8
1.9
100
–
–
0.8
–
–
0.8
–
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–
–
0.8
–
DIFF_HSTL_I
1.4
1.5
1.6
100
–
–
0.68
–
DIFF_HSTL_III
1.4
1.5
1.6
100
–
–
–
0.9
DIFF_SSTL18_I
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–
1.7
1.8
1.9
100
–
–
0.7
–
–
0.7
–
DIFF_SSTL2_I
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–
2.3
2.5
2.7
100
–
–
1.0
–
–
1.0
–
DIFF_SSTL3_I
3.0
3.3
3.6
100
–
–
1.1
–
DIFF_SSTL3_II
3.0
3.3
3.6
100
–
–
1.1
–
Max (V)
2.35
2.35
2.35
1.95
1.95
1.95
2.8(6)
1.5
1.5
3.23
2.3
2.3
1.1
1.1
1.1
0.9
–
1.1
1.1
1.5
1.5
1.9
1.9
Notes:
1. The VCCO rails supply only differential output drivers, not input circuits.
2. VICM must be less than VCCAUX.
3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
4. See "External Termination Requirements for Differential I/O."
5. LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX = 3.3V ± 10%.
6. LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID/2).
7. Requires VCCAUX = 3.3V ±10%. (VCCAUX - 300 mV) ≤ VICM ≤ (VCCAUX - 37 mV).
8. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
9. All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.
DS610 (v3.0) October 4, 2010
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Product Specification
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