XC3SD3400A-4FGG676C Datasheet, PDF (84/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 67 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3SD1800A in the FG676 Package
Package
Edge
I/O Bank
Maximum I/Os
and
Input-Only
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF⁽¹⁾
Top
0
128
82
28
1
9
Right
1
130
67
15
30
10
Bottom
2
129
68
21
21
11
Left
3
132
97
18
0
9
TOTAL
519
314
82
52
39
CLK
8
8
8
8
32
Notes:
1. 28 VREF are on INPUT pins.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
84