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XC3SD3400A-4FGG676C Datasheet, PDF (37/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Package Type
Signal Standard
(IOSTANDARD)
CS484, FG676
Top, Bottom Left, Right
(Banks 0, 2) (Banks 1, 3)
LVCMOS12
Slow
2
40
40
4
–
25
6
–
18
Fast
2
31
31
4
–
13
6
–
9
QuietIO 2
55
55
4
–
36
6
–
36
PCI33_3
16
16
PCI66_3
–
13
HSTL_I
–
20
HSTL_III
–
8
HSTL_I_18
17
17
HSTL_II_18
–
5
HSTL_III_18
10
8
SSTL18_I
7
15
SSTL18_II
–
9
SSTL2_I
18
18
SSTL2_II
–
9
SSTL3_I
8
10
SSTL3_II
6
7
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Package Type
Signal Standard
(IOSTANDARD)
CS484, FG676
Top, Bottom Left, Right
(Banks 0, 2) (Banks 1, 3)
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
22
–
LVDS_33
27
–
BLVDS_25
4
4
MINI_LVDS_25
22
–
MINI_LVDS_33
27
–
LVPECL_25
Inputs Only
LVPECL_33
Inputs Only
RSDS_25
22
–
RSDS_33
27
–
TMDS_33
27
–
PPDS_25
22
–
PPDS_33
27
–
DIFF_HSTL_I_18
8
8
DIFF_HSTL_II_18
–
2
DIFF_HSTL_III_18
5
4
DIFF_HSTL_I
–
10
DIFF_HSTL_III
–
4
DIFF_SSTL18_I
3
7
DIFF_SSTL18_II
–
4
DIFF_SSTL2_I
9
9
DIFF_SSTL2_II
–
4
DIFF_SSTL3_I
4
5
DIFF_SSTL3_II
3
3
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2. The numbers in this table are recommendations that assume
sound board lay out practice. This table assumes the following
parasitic factors: combined PCB trace and land inductance per
VCCO and GND pin of 1.0 nH, receiver capacitive load of 15 pF.
Test limits are the VIL/VIH voltage limits for the respective I/O
standard.
3. If more than one signal standard is assigned to the I/Os of a
given bank, refer to XAPP689: Managing Ground Bounce in
Large FPGAs for information on how to perform weighted
average SSO calculations.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
37
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