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XC3SD3400A-4FGG676C Datasheet, PDF (50/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Suspend Mode Timing
X-Ref Target - Figure 9
Entering Suspend Mode
SUSPEND Input
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
tSUSPEND_GWE
tAWAKE_GWE
Write Protected
tSUSPEND_GTS
tAWAKE_GTS
Defined by SUSPEND constraint
tSUSPEND_DISABLE
tSUSPEND_ENABLE
Blocked
Figure 9: Suspend Mode Timing
DS610-3_08_061207
Table 44: Suspend Mode Timing Parameters
Symbol
Description
Min Typ Max Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter –
7
– ns
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
+160 +300 +600 ns
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
– ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
–
<5
– ns
elements
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
–
340
– ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not – 4 to 108 –
μs
include DCM lock time.
TSUSPEND_ENABLE
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
– 3.7 to 109 – μs
TAWAKE_GWE1
Rising edge of the AWAKE pin until write-protect lock released on all writable –
67
– ns
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
TAWAKE_GWE512
Rising edge of the AWAKE pin until write-protect lock released on all writable –
14
– µs
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
TAWAKE_GTS1
Rising edge of the AWAKE pin until outputs return to the behavior described –
57
– ns
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described –
14
– µs
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3A DSP Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
50