XC3SD3400A-4FGG676C Datasheet, PDF (53/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 47: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
Minimum
F_CCLK1
Equivalent CCLK clock frequency
1
by ConfigRate setting
(power-on value)
Commercial
Industrial
0.400
F_CCLK3
Commercial
3
1.20
Industrial
F_CCLK6
6
(default)
Commercial
Industrial
2.40
F_CCLK7
Commercial
7
2.80
Industrial
F_CCLK8
Commercial
8
3.20
Industrial
F_CCLK10
Commercial
10
4.00
Industrial
F_CCLK12
Commercial
12
4.80
Industrial
F_CCLK13
Commercial
13
5.20
Industrial
F_CCLK17
Commercial
17
6.80
Industrial
F_CCLK22
Commercial
22
8.80
Industrial
F_CCLK25
Commercial
25
10.00
Industrial
F_CCLK27
Commercial
27
10.80
Industrial
F_CCLK33
Commercial
33
13.20
Industrial
F_CCLK44
Commercial
44
17.60
Industrial
F_CCLK50
Commercial
50
20.00
Industrial
F_CCLK100
Commercial
100
40.00
Industrial
Maximum
0.797
0.847
2.42
2.57
4.83
5.13
5.61
5.96
6.41
6.81
8.12
8.63
9.70
10.31
10.69
11.37
13.74
14.61
18.44
19.61
20.90
22.23
22.39
23.81
27.48
29.23
37.60
40.00
44.80
47.66
88.68
94.34
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 48: Master Mode CCLK Output Minimum Low and High Time
Symbol
Description
ConfigRate Setting
Units
1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100
T_MCCL, Master Mode _{Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns}
T_MCCH
CCLK
Minimum
Low and High Industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns
Time
Table 49: Slave Mode CCLK Input Low and High Time
Symbol
Description
T_SCCL
T_SCCH
CCLK Low and High time
Min
Max
Units
5
∞
ns
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
53