XC3SD3400A-4FGG676C Datasheet, PDF (45/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 37: Switching Characteristics for the DLL
Symbol
Description
Output Frequency Ranges
CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs
CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
CLKOUT_FREQ_DV
Frequency for the CLKDV output
Output Clock Jitter ^(2)(3)(4)
CLKOUT_PER_JITT_0 Period jitter at the CLK0 output
CLKOUT_PER_JITT_90 Period jitter at the CLK90 output
CLKOUT_PER_JITT_180 Period jitter at the CLK180 output
CLKOUT_PER_JITT_270 Period jitter at the CLK270 output
CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs
CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing
integer division
CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing
non-integer division
Duty Cycle ⁽⁴⁾
CLKOUT_DUTY_CYCLE_ Duty cycle variation for the CLK0, CLK90, CLK180,
DLL
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Phase Alignment ⁽⁴⁾
CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs
CLKOUT_PHASE_DLL
Phase offset between DLL
outputs
CLK0 to CLK2X
(not CLK2X180)
All others
Lock Time
LOCK_DLL⁽³⁾
When using the DLL alone:
The time from deassertion at
the DCM’s Reset input to the
rising transition at its LOCKED
output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase
5 MHz < FCLKIN <
15 MHz
FCLKIN > 15 MHz
Device
Speed Grade
-5
-4
Min Max Min Max
Units
All
5
280
5
250 MHz
5
200
5
200 MHz
10 334 10 334 MHz
0.3125 186 0.3125 166 MHz
All
– ±100 – ±100 ps
– ±150 – ±150 ps
– ±150 – ±150 ps
– ±150 – ±150 ps
– ±[0.5% – ±[0.5% ps
of
of
CLKIN
CLKIN
period
period
+ 100]
+ 100]
– ±150 – ±150 ps
– ±[0.5% – ±[0.5% ps
of
of
CLKIN
CLKIN
period
period
+ 100]
+ 100]
All
– ±[1% of – ±[1% of ps
CLKIN
CLKIN
period
period
+ 350]
+ 350]
All
– ±150 – ±150 ps
– ±[1% of – ±[1% of ps
CLKIN
CLKIN
period
period
+ 100]
+ 100]
– ±[1% of – ±[1% of ps
CLKIN
CLKIN
period
period
+ 150]
+ 150]
All
–
5
–
5
ms
–
600
–
600 µs
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
45