XC3SD3400A-4FGG676C Datasheet, PDF (21/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 18: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Setup Times
T_PSDCM
When writing to the Input
LVCMOS25⁽²⁾,
XC3SD1800A
2.65
Flip-Flop (IFF), the time from IFD_DELAY_VALUE = 0,
the setup of data at the Input pin with DCM⁽⁴⁾
XC3SD3400A
2.25
3.11
2.49
to the active transition at a
Global Clock pin. The DCM is in
use. No Input Delay is
programmed.
T_PSFD
When writing to IFF, the time LVCMOS25⁽²⁾,
XC3SD1800A
2.98
3.39
from the setup of data at the IFD_DELAY_VALUE = 6,
Input pin to an active transition without DCM
XC3SD3400A
2.78
3.08
at the Global Clock pin. The
DCM is not in use. The Input
Delay is programmed.
Hold Times
T_PHDCM
T_PHFD
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is in use.
No Input Delay is programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not in
use. The Input Delay is
programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 6,
without DCM
XC3SD1800A
XC3SD3400A
–0.38
–0.26
XC3SD1800A
XC3SD3400A
–0.71
–0.65
–0.38
–0.26
–0.71
–0.65
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
21