XC3SD3400A-4FGG676C Datasheet, PDF (47/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 39: Switching Characteristics for the DFS
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min Max Min Max
Output Frequency Ranges
CLKOUT_FREQ_FX⁽²⁾ Frequency for the CLKFX and CLKFX180 outputs
Output Clock Jitter ⁽³⁾⁽⁴⁾
All
5
350
5
311 MHz
CLKOUT_PER_JITT_FX Period jitter at the CLKFX and
CLKFX180 outputs.
CLKIN
≤ 20 MHz
All Typ Max Typ Max
Use the Spartan-3A Jitter Calculator: ps
www.xilinx.com/support/documentation/
data_sheets/s3a_jitter_calc.zip
Duty Cycle⁽⁵⁾⁽⁶⁾
CLKIN
> 20 MHz
±[1% of ±[1% of ±[1% of ±[1% of ps
CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
CLKOUT_DUTY_CYCLE_ Duty cycle precision for the CLKFX and CLKFX180
All
– ±[1% of – ±[1% of ps
FX
outputs, including the BUFGMUX and clock tree
CLKFX
CLKFX
duty-cycle distortion
period
period
+ 350]
+ 350]
Phase Alignment⁽⁶⁾
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the All
DLL CLK0 output when both the DFS and DLL are used
–
±200
–
±200 ps
CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and All
the DLL CLK0 output when both the DFS and DLL are
used
– ±[1% of – ±[1% of ps
CLKFX
CLKFX
period
period
+ 200]
+ 200]
Lock Time
LOCK_FX ⁽²⁾⁽³⁾
The time from deassertion at the
5 MHz < F_CLKIN All
–
5
–
5
ms
DCM’s Reset input to the rising
< 15 MHz
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
F_CLKIN >
15 MHz
–
450
–
450 µs
valid. If using both the DLL and the
DFS, use the longer locking time.
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7 and Table 38.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization,
CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system
application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
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