XC3SD3400A-4FGG676C Datasheet, PDF (58/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 14
PROG_B
(Input)
PUDC_B
(Input)
M[2:0]
(Input)
INIT_B
(Open-Drain)
LDC[2:0]
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T_MINIT
<0:1:0>
T_INITM
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
HDC
CSO_B
New ConfigRate active
CCLK
A[25:0]
D[7:0]
(Input)
T_CCLK1
T _INITADDR
000_0000
Byte 0
000_0001
Byte 1
T_CCLK1
T_CCLKn
T_AVQV
Data
T_CCO
Address
Address Address
T_DCC
Data
Data
T_CCD
Data
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
DS529-3_05_090610
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
T_INITM
T_INITADDR
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
T_CCO
T_DCC
T_CCD
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Minimum Maximum Units
See Table 46
See Table 46
50
–
ns
0
–
ns
5
5
T_CCLK1
cycles
See Table 50
See T_SMDCC in Table 51
0
–
ns
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
58