XC3SD3400A-4FGG676C Datasheet, PDF (60/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
IEEE 1149.1/1532 JTAG Test Access Port Timing
X-Ref Target - Figure 15
TCK
(Input)
TMS
(Input)
T_TMSTCK
T_TDITCK
T_TCKTMS
T_TCKTDI
T_CCH
T_CCL
1/F_TCK
TDI
(Input)
TDO
(Output)
T_TCKTDO
Figure 15: JTAG Waveforms
DS099_06_090610
Table 56: Timing for the JTAG⁽²⁾ Test Access Port
Symbol
Description
Clock-to-Output Times
T_TCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
Setup Times
T_TDITCK
The time from the setup of data at the All functions except those shown below
TDI pin to the rising transition at the
TCK pin
Boundary scan commands
(INTEST, EXTEST, SAMPLE)
T_TMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
Hold Times
T_TCKTDI The time from the rising transition at All functions except those shown below
the TCK pin to the point when data is
last held at the TDI pin
Configuration commands (CFG_IN, ISC_PROGRAM)
T_TCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
Clock Timing
T_CCH
The High pulse width at the TCK pin
T_CCL
The Low pulse width at the TCK pin
T_CCHDNA The High pulse width at the TCK pin
T_CCLDNA The Low pulse width at the TCK pin
F_TCK
Frequency of the TCK signal
All functions except ISC_DNA command
During ISC_DNA command
BYPASS or HIGHZ instructions
All operations except for BYPASS or HIGHZ instructions
All Speed
Grades
Min Max
Units
1.0
11.0 ns
7.0
–
ns
13.0
7.0
–
ns
0
–
ns
3.5
0
–
ns
5
–
ns
5
–
ns
10 10,000 ns
10 10,000 ns
0
33 MHz
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7.
2. For details on JTAG, see Chapter 9, “JTAG Configuraton Mode and Boundary-Scan” in UG332: Spartan-3 Generation Configuration User
Guide.
DS610 (v3.0) October 4, 2010
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Product Specification
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