XC3SD3400A-4FGG676C Datasheet, PDF(97/101 Page) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

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XC3SD3400A-4FGG676C Datasheet, PDF (97/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

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Spartan-3A DSP FPGA Family: Pinout Descriptions

FG676 Footprint â

XC3SD3400A FPGA

Left Half of Package

(Top View)

I/O: Unrestricted,

314 general-purpose user I/O.

INPUT: Unrestricted,

34 general-purpose input pin.

DUAL: Configuration pins,

51 then possible user I/O.

VREF: User I/O or input

37 voltage reference for bank.

CLK: User I/O, input, or

32 clock buffer input.

CONFIG: Dedicated

2 configuration pins.

SUSPEND: Dedicated

2 SUSPEND and

dual-purpose AWAKE

Power Management pins

JTAG: Dedicated JTAG

4 port pins.

GND

PROG_ I/O

L51P_0

I/O

L45P_0

GND

Bank 0

VCCO_0 I/O

I/O

L38P_0 L36P_0

I/O

L33P_0

GND

12 13

I/O INPUT

L29P_0

I/O

L02N_3

I/O

L02P_3

I/O

L51N_0

I/O VCCO_0 I/O

L45N_0

L41P_0

INPUT VCCO_3

C VREF_3

GND

VCCINT I/O

L44P_0

I/O

L41N_0

VCCAUX GND

Dâ â

I/O

L06P_3

â VCCINT

TMS

I/O

L44N_0

I/O

L42P_0

I/O

L42N_0

INPUT

VREF_0

I/O

L38N_0

I/O

L40P_0

I/O

L40N_0

I/O

L36N_0

GND

I/O

L37N_0

I/O VCCO_0 I/O

L33N_0

L29N_0

I/O

L34P_0 L32P_0 L30N_0

I/O

L34N_0

I/O

L32N_0

VREF_0

INPUT

I/O

L28P_0

GCLK10

I/O

L28N_0

GCLK11

I/O

L30P_0

I/O

L11P_3

VCCO_3

I/O

L07P_3

â I/O

VCCINT

VCCAUX

I/O

VCCO_0

L06N_3

L48N_0

GND

I/O

INPUT

I/O VCCO_0

L37P_0

L31P_0

GND

I/O

L11N_3 L14N_3 L07N_3 L09P_3

GND

I/O

L48P_0

I/O VCCAUX VCCINT

L52P_0

VREF_0

GND

I/O

L31N_0

I/O

L27P_0

GCLK8

INPUT

Gâ

H I/O

L17N_3

INPUT

L24P_3

GND

I/O

L17P_3

INPUT

L20N_3

VREF_3

I/O

L14P_3

GND

INPUT

L20P_3

I/O

L09N_3

GND

I/O

L03P_3

INPUT

VREF_3

VCCO_3

I/O

L10N_3

I/O

L19N_3 L19P_3 L13N_3

TDI

I/O

L52N_0

PUDC_B

I/O

L47P_0

I/O

GND

I/O

L03N_3

L47N_0

I/O

L10P_3 L01P_3 L01N_3

I/O INPUT I/O

L46P_0 VREF_0 L35P_0

I/O VCCO_0 I/O

L46N_0

L35N_0

INPUT I/O

I/O

L43P_0 L39P_0

I/O

L27N_0

GCLK9

INPUT

L24N_3

I/O

L23N_3

I/O

L23P_3

I/O

L22N_3

I/O

L22P_3

I/O

L18P_3

I/O

L13P_3

I/O

L05N_3

I/O

L05P_3

GND

I/O

I/O VCCAUX

L43N_0 L39N_0

GND VCCO_3 I/O

I/O VCCAUX GND

L25N_3 L25P_3

I/O VCCO_3 I/O

I/O

L18N_3

L15N_3 L15P_3

GND VCCINT GND

I/O

M L29N_3

VREF_3

I/O

L31P_3

I/O

P L33P_3

LHCLK2

I/O

R L36P_3

VREF_3

I/O

L29P_3

I/O

L31N_3

I/O

L33N_3

IRDY2

LHCLK3

I/O

L36N_3

I/O

L27N_3

GND

I/O

L34N_3

LHCLK5

I/O

L37P_3

I/O

L27P_3 L28P_3 L28N_3

I/O

L30N_3

I/O

L30P_3

I/O

L32P_3

LHCLK0

I/O

L34P_3

LHCLK4

VCCO_3

I/O

L39N_3

I/O

L37N_3 L40P_3 L40N_3

I/O

L26N_3

I/O

L32N_3

LHCLK1

I/O

L39P_3

I/O

L45N_3

I/O

L26P_3

GND

I/O

L41P_3

I/O

L45P_3

I/O

I/O VCCINT GND VCCINT

L21N_3 L21P_3

I/O

L35P_3

TRDY2

LHCLK6

I/O

L41N_3

VCCAUX GND VCCINT VCCINT

I/O

L35N_3 VCCINT

LHCLK7

GND

VCCINT

I/O

L43N_3

I/O

L43P_3

VREF_3

GND VCCINT GND

T GND VCCO_3 I/O

I/O

GND

I/O VCCO_3 I/O

I/O VCCINT GND VCCINT

L38P_3 L38N_3 L42P_3

L51P_3

L48N_3 L48P_3

GND: Ground

100

VCCO: Output voltage

40 supply for bank.

VCCINT: Internal core

36 supply voltage (+1.2V).

VCCAUX: Auxiliary supply

24 voltage.

Note: The boxes with

question marks inside

indicate pin differences

from the XC3SD1800A

device. Please see the

Footprint Migration

Differences section for more

information.

U I/O

I/O INPUT I/O

I/O

GND

I/O VCCINT GND

L44P_3 L44N_3 L46P_3 L42N_3 L49P_3 L51N_3 L56P_3 L56N_3 L61P_3

L13N_2

I/O

L47P_3

I/O

L47N_3

GND

INPUT I/O

I/O

I/O VCCAUX I/O

I/O

L46N_3 L49N_3 L59N_3 L59P_3 L61N_3

L09P_2 L13P_2 L16P_2 L20P_2

INPUT

L50P_3

INPUT

L50N_3

VREF_3

I/O

L52P_3

I/O VCCO_3 I/O

L52N_3

L63N_3

I/O

L63P_3

GND

I/O

I/O VCCO_2 I/O

I/O

L05P_2 L09N_2

L16N_2 L20N_2

I/O

L53P_3

GND

I/O

L53N_3

I/O

L55P_3

INPUT VCCINT I/O

L57P_3

I/O

L55N_3

GND

INPUT

VREF_3

I/O

L57N_3

GND

I/O VCCINT I/O

L02P_2

L05N_2

I/O VCCINT INPUT

L02N_2

CSO_B

VREF_2

I/O VCCINT I/O

I/O

L12P_2

L17P_2 L25N_2

RDWR_B GCLK13

I/O

L12N_2

GND

I/O

L17N_2

VS2

I/O

L25P_2

GCLK12

I/O

VCCO_3

B L60P_3

GND

â VCCAUX

VCCAUX

INPUT

I/O VCCO_2 I/O

VREF_2 L14N_2

L15P_2

GND

VCCAUX I/O

L21P_2

INPUT

A I/O

I/O

C L60N_3 L64P_3 L64N_3

A I/O

I/O

D L65P_3 L65N_3

GND

A INPUT INPUT I/O

L66P_3

L66N_3

VREF_3

L06P_2

GND

VCCAUX I/O

L06N_2

I/O

L01P_2

I/O

L01N_2

GND

I/O

L08P_2

GND

I/O

L14P_2

I/O

GND

L08N_2 L11P_2

I/O VCCO_2 I/O

I/O

L07P_2

L10N_2 L11N_2 L18P_2

I/O

L07N_2 L10P_2

GND

VCCO_2 I/O

L18N_2

I/O

L15N_2

INPUT

I/O

L19P_2

VS1

I/O

L19N_2

VS0

INPUT I/O

I/O INPUT

VREF_2 L23N_2 L21N_2

INPUT I/O INPUT GND

L23P_2 VREF_2

I/O

L22P_2

VCCO_2

I/O

L24N_2

I/O

L26N_2

GCLK15

I/O

L22N_2

GND

I/O

L24P_2

I/O

L26P_2

GCLK14

Bank 2

Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top ViewâLeft Half)

DS610 (v3.0) October 4, 2010

www.xilinx.com

Product Specification

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